“The triangle processor and normal vector shader: a VLSI system for high performance graphics” by Deering, Winner, Schediwy, Duffy and Hunt
Conference:
Type(s):
Title:
- The triangle processor and normal vector shader: a VLSI system for high performance graphics
Presenter(s)/Author(s):
Abstract:
Current affordable architectures for high-speed display of shaded 3D objects operate orders of magnitude too slowly. Recent advances in floating point chip technology have outpaced polygon fill time, making the memory access bottleneck between the drawing processor and the frame buffer the most significant factor to be accelerated. Massively parallel VLSI system have the potential to bypass this bottleneck, but to date only at very high cost. We describe a new more affordable VLSI solution. A pipeline of triangle processors rasterizes the geometry, then a further pipeline of shading processors applies Phong shading with multiple light sources. The triangle processor pipeline performs 100 billion additions per second, and the shading pipeline performs two billion multiplies per second. This allows 3D graphics systems to be built capable of displaying more than one million triangles per second. We show the results of an anti-aliasing technique, and discuss extensions to texture mapping, shadows, and environment maps.
References:
1. Gary Bishop and David M. Weimer. Fast Phong shading. Proceedings of SIGGRAPH’86 (Dallas, Texas, August 18-22, 1986). In Computer Graphics, pages 103-106, 1986.
2. James. H. Clark. The geometry engine, a VLSI geometry system for graphics. Proceedings of SIC- GRAPH’82 (Boston, Massachusetts, July 26-30, 1982). In Computer Graphics, pages 127-133, 1982.
3. Robert. L. Cook. Stochastic sampling in computer graphics. A CM Transactions on Computer Graphics, 5(1):51-72, January 1986.
4. Stefan Demetreseu. High speed image rasterizatlon using scan llne access memories. In 1985 Chapel Hill Conference on Very .Large Scale Integration, pages 221-243, Computer Science Press, 1985.
5. Henry Fuchs and John Poulton. Pixel-planes: a VLSI-oriented design for a raster graphics engine. VLSI Design, 2(3):20-28, 1981.
6. Nader Gharachorloo and Christopher Pottle. SUPER BUFFER: a systolic VLSI graphics engine for real time raster image generation. In 1985 Chapel Hill Conference on Very Large Scale Integration, pages 285-305, Computer Science Press, 1985.
7. Paul S. Heckbert. Survey of texture mapping. IEEE Computer Graphics and Applications, 6(11):56- 67, November 1986.
8. Adam Levinthal and Thomas Porter. Chap – a SIMD graphics processor. Proceedings of SIC- GRAPH’84 (Minneapolis, Minnesota, July 23-27, 1984). In Computer Graphics, pages 77-82, 1984.
9. Leonard MeMillan. Graphics at 820 MFLOPS. ESD: THE Electronic Systems Design Magazine, 17(9):87-95, September 1987.
10. Teiji Nishlzawa et al. A hidden surface processor for 3-dimension graphics. In Proceedings of ISSCC’88, pages 166-167,351, 1988.
11. John Poulton et al. PIXEL-PLANES: building a VLSI-based graphic system. In 1985 Chapel Hill Conference on Very Large Scale Integratlon, pages 35-60, Computer Science Press, 1985.
12. William T. Reeves, David H. Salesin, and Robert L. Cook. Rendering antialiased shadows with depth maps. Proceedings of SIGGRAPH’87 (Anaheim, California, July 27-31, 1987). In Computer Graphics, pages 283-291, 1987.
13. Roger W. Swanson and Larry J. Thayer. A fast shaded-polygon renderer. Proceedings of SIG- GRAPH’86 (Dallas, Texas, August 18-22, 1986). In Computer Graphics, pages 95-101, 1986.
14. John G. Torborg. A parallel processor architecture for graphics arithmetic operations. Proceedings of SIGGRAPH’87 (Anaheim, California, July 27-31, 1987). In Computer Graphics, pages 197-204, 1987.
15. Andries van Dam et al. PHIGS+ functional description rev. 2.0. July 20 1987. Jointly developed PHIGS+ specification.