“Simulation and expected performance analysis of multiple processor Z-buffer systems” by Parke

  • ©Frederic (Fred) I. Parke

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Title:

    Simulation and expected performance analysis of multiple processor Z-buffer systems

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Abstract:


    The results of expected performance analysis and simulation of three multiple processor Z-buffer architectures are presented. These architectures have been proposed as approaches to applying many processors, working in parallel, to the task of rapidly creating shaded raster images. These architectures are attractive since they offer potentially high performance, in terms of image update rate, at modest cost. All three approaches make use of multiple instances of identical processor modules. The analyses and simulations indicate that substantial gain is possible by applying multiple processors to the task. But, as more and more processors are added, additional gains in performance become smaller and smaller. This result suggests optimal system sizes. The performance of these architectures depends on the processors used, the number of processors, and certain characteristics of the image environments. Each architecture has its own performance characteristics and limitations.

References:


    1. I. E. Sutherland, R. F. Sproull, R. A. Schumacker, “A Characterization of Ten Hidden Surface Algorithms,” Computing Surveys, March 1974.
    2. W. M. Newman and R. F. Sproull, Principles of Interactive Computer Graphics, McGraw-Hill, 2nd Ed., 1979.
    3. H. Fuchs, “Distributing a Visible Surface Algorithm Over Multiple Processors,” Proc. ACM ’77, Seattle, Oct. 1977.
    4. H. Fuchs and B. Johnson, “An Expandable Architecture for Video Graphics,” Proc. 6th Symp. on Comp. Arch., April 1979.
    5. F. I. Parke, “A Parallel Architecture for Shaded Graphics,” Tech. Rep., Computer Engineering Dept., Case Western Reserve Univ., Jan. 1979.
    6. I. E. Sutherland and G. W. Hodgeman, “Reentrant Polygon Clipping,” CACM, June 1974.
    7. F. C. Crow, “The Aliasing Problem in Computer Synthesized Shaded Images,” CACM, Nov. 1977. Also Tech. Rep. UTEC-CSc-76-015, Univ. of Utah, March 1976.
    8. F. I. Parke, “Performance Analysis of Z-buffer Convex Tiler Based Shaded Image Generation,” Tech. Rep. CES 79-15, Computer Engineering, Case Institute of Technology, Oct. 1979.
    9. F. I. Parke, “An Introduction to the N.mPc Design Environment,” Proc. 16th Design Automation Conf., San Diego, June 1979.


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