“PixelFlow: high-speed rendering using image composition” by Molnar, Eyles and Poulton
Conference:
Type(s):
Title:
- PixelFlow: high-speed rendering using image composition
Presenter(s)/Author(s):
Abstract:
No abstract available.
References:
1. Akeley, K. and T. Jermoluk, “High-Performance Polygon Rendering,” SIGGRAPH ’88, Vol. 22, No. 4, pp. 239-246.
2. Apgar, B., B. Bersack, and A. Mammen, “A Display System for the Stellar Graphics Supercomputer Model GS 1000,” SIGGRAPH ’88, Vol. 22, No. 4, pp. 255-262.
3. Bunker, M. and R. Economy, “Evolution of GE CIG Systems,” SCSD Document, General Electric Company, Daytona Beach, FL 32015, 1989.
4. Deering, M., S. Winner, B. Schediwy, C. Duffy, and N. Hunt, “The Triangle Processor and Normal Vector Shader: A VLSI System for High Performance Graphics,” SIGGRAPH ’88, Vol. 22, No. 4, pp. 21- 30.
5. Demetrescu, S., A VLSl-Based Real-Time Hidden- Surface Elimination Display System, Master’s Thesis, Dept. of Computer Science, California Institute of Technology, 1980.
6. Duff, T., “Compositing 3D Rendered Images,” SIGGRAPH ’85, Vol. 19, No. 3, July 1985, pp. 41-44.
7. Ellis, J., G. Kedem, T. Lyerly, D. Thielman, R. Marisa, J. Menon, H. Voelcker, “The Raycasting Engine and Ray Representation: A Technical Summary,” Proc. of the Intl. Jornal of Cornputational Geometn’ and Applications, 1991.
8. Ellsworth, D.E., H. Good, and B. Tebbs, “Distributing Display Lists on a Multicomputer,” Computer Graphics (Proceedings of the 1990 Symposium on Interactive 3D Graphics), Vol. 24, No. 2, March 1990, p.147-154.
9. Ellsworth, D.E. “Parallel Architectures and Algorithms for Real-Time Synthesis of High-Quality Images Using Deferred Shading,” Workshop on Algorithms and Parallel VLSI Architectures, Pont-a- Mousson, France, June 12, 1990.
10. Eyles, J., J. Austin, H. Fuchs, T. Greer, and J. Poulton, “Pixel-Planes 4: A Summary,” Adv. in Computer Graphics Hardware H (1987 Eurographics Workshop on Graphics Hardware), Eurographics Seminars, 1988, pp. 183-208.
11. Foley, J.D., A. van Dam, S.K. Feiner, and J.F. Hughes, Computer Graphics: Principles and Practice, Addison-Wesley, Reading, MA, 1990. (especially Chapter 18, “Advanced Raster Graphics Architecture”)
12. Fuchs, H., “Distributing a Visible Surface Algorithm over Multiple Processors,” Proceedings of the ACM Annual Conference, pp. 449-451.
13. H. and B. Johnson, prepublication &all of”An Expandable Multiprocessor Architecture for Video Graphics,” Proceedings of the 6th ACM-IEEE Symposium on Computer Architecture, April, 1979, pp. 58-67.
14. Fuchs, H., J. Goldfeather, J. Hultquist, S. Spach, J. Austin, F. Brooks, J. Eyles, and J. Poulton, “Fast Spheres, Shadows, Textures, Transparencies, and Image Enhancements in Pixel-planes,” SIGGRAPH ’85, Vol. 19, No. 3, pp. 111-120.
15. Fuchs, H., J. Poulton, J. Eyles, T. Greer, J. Goldfeather, D. Ellsworth, S. Molnar, G. Turk, B. Tebbs, and L. Israel, “PixeI-Planes 5: A Heterogeneous Multiprocessor Graphics System Using Processor-Enhanced Memories,” SIGGRAPH ’89, Vol. 23, No. 3, pp. 79-88.
16. Fussel, D. and B. D. Rathi, “A VLSI-Oriented Architecture for Real-Time Raster Display of Shaded Polygons.” Graphics Interface ’82, 1982, pp. 373- 380.
17. Gardner, G.Y., E.P. Berlin, Jr., and B.M. Gelman, “A Real-Time Computer image Generation System using Textured Curved Surfaces,” Proceedings of IMAGE II, 1981, pp. 59-76.
18. Gharachorloo, N., S. Gupta, E. Hokenek, P. Balasubramanian, B. Bogholtz, C. Mathieu, and C. Zoulas, “Subnanosecond Pixel Rendering with Million Transistor Chips,” SIGGRAPH 88, Vol. 22, No. 4, pp. 41-49.
19. Knight, T. and A. Krimm, “A Self-Terminating Low- Voltage Swing CMOS Output Driver,” IEEE Journal of Solid-State Circuits, Vol. 23, No. 2, April 1988, pp. 457-464.
20. Martin, P., and H. Baeverstad, “TurboVRX: A High- Performance Graphics Workstation Architecture,” Proc. of A USGtL4PH 90, September 1990, pp. 107- 117.
21. Molnar, S.E., “Combining Z-buffer Engines for Higher-Speed Rendering,” Advances in Computer Graphics Hardware 111, Eurographics Seminars, 1988, pp. 171-182.
22. Molnar, S.E., “Efficient Supersampling Antialiasing for High-Performance Architectures,” Technical Report TR-91-023, Dept. of Computer Science, UNC-Chapel Hill, 199 i.
23. Motnar, S.E., “Image Composition Architectures for Real-Time Image Generation,” Ph.D. dissertation, also available as UNC-Computer Science Technical Report TR91-046, 1991.
24. Park, F., “Simulation and Expected Performance Analysis of Multiple Processor Z-Buffer Systems,” SIGGRAPH ’80, Vol. 14, No. 3, pp. 48-56.
25. Potmesil, M., and E. Hoffert, “The Pixel Machine: A Parallel Image Computer,” SIGGRAPH ’89, Vol. 23, No. 3, pp. 69-78.
26. Poulton, J., H. Fuchs, and A. Paeth, “Pixel-planes graphic engine,” Section 9.5 in Principles of CMOS VLSI Design: A System Perspective, by Neil Weste and Kamran Eshrahian, Addison-Wesley, New York, 1985, pp. 448-480.
27. Silicon Graphics Computer Systems, Vision Graphics System Architecture, Mountain View, CA 94039- 7311, February 1990.
28. Shaw, C.D., M. Green, and J. Schaeffer, “A VLSI Architecture for Image Composition,” Advances in Computer Graphics Hardware 111,, Eurographics Seminars, 1988, pp. 183-199.
29. Speck, D., “The Mosaic Fast 512K Scalable CMOS DRAM,” Proceedings of the 1991 University of California at Santa Cruz Conference on Advanced Research in VLSI, 1991, pp. 229-244.
30. Schneider, B.O. and U. Claussen, “PROOF: An Architecture for Rendering in Object-Space,” Advances in Computer Graphics Hardware 111, Eurographics Seminars, 1988, pp. 121-140.
31. Weinberg, R., “Parallel Processing Image Synthesis and Anti-Aliasing,” SIGGRAPH ’81, Vol. 15, No. 3, pp. 55-61.