“High-performance raster graphics for microcomputer systems” by Bechtolsheim and Baskett

  • ©Andreas Bechtolsheim and Forest Baskett




    High-performance raster graphics for microcomputer systems



    A frame buffer architecture is presented that reduces the overhead of frame buffer updating by three means. First, the bit-map memory is (x,y) addressable, whereby a string of pixels can be accessed in parallel. Second, the pixel-change operation is performed by hardware in a single read-modify-write cycle. Third, multiple objects in the frame buffer are addressable simultaneously by a set of address registers. The remaining task of generating (x,y) addresses and providing new data can be managed rapidly by current microprocessors or DMA-devices. With a modest expenditure of hardware, this architecture eliminates all the bit-shifting, bit-masking, and bit-manipulation conventionally associated with frame buffer graphics, while retaining the full generality of user-programmable control. The particular implementation described allows raster manipulation at full bit-map memory bandwidth. It can paint a 16×16 pixel character into the frame buffer in 16 microseconds and can modify a 1024×1024 pixel raster in 64 milliseconds.


    1. W.M. Newman and R.F. Sproull, Principles of Interactive Computer Graphics, second edition, McGraw Hill, 1979.
    2. C.P. Thacker, et al., “Alto: A personal Computer”, in D. Siewiorek, C.G. Bell and A. Newell, Computer Structures: Readings and Examples, second edition, McGraw Hill, 1980.
    3. I.E. Sutherland, R.F. Sproull, S. Gupta, A. Thompson, personal communication.
    4. R.F. Sproull “Raster Graphics for Interactive Programming Environments”, Xerox PARC Report CSL-79-6, June 1979.

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