“A Portable, Reusable Framework for Scientific Computing on GPUs” by Payne, Owen, Weber, Zhu and Liu

  • ©Bryson R. Payne, G. Scott Owen, Irene Weber, Ying Zhu, and Ping Liu



Entry Number: 093


    A Portable, Reusable Framework for Scientific Computing on GPUs



    Programmable graphics processing units (GPUs) are commonly included as hardware components in new computer workstations, including those workstations used for scientific computing. The current generation of GPU is roughly equivalent in processing power to current CPUs (Central Processing Units), but that power is rarely used to its full capabilities in an average scientific workstation. Numerous advances have been made recently in applying the GPU to parallel matrix processing tasks, such as the Fast Fourier Transform (FFT) [Moreland and Angel 2003].
    Our primary goal is to produce a reusable, portable framework [Thompson et al. 2002] for applying GPU-accelerated computation to scientific computing problems. Our secondary goal to apply GPU-accelerated computation to a specific scientific computing problem to serve as a model: automated structure fitting in protein crystallography, a process that normally takes several hours or even days to execute on a sequential CPU.


    1. Badger, J. 2003. An evaluation of automated model-building procedures for protein crystallography. Acta Crystallographica, 823–827.
    2. Lamzin, V. S. and Wilson, K. S. 1997. Automated refinement for protein crystallography. Methods in Enzymology, 277(B), 269–305.
    3. Moreland, K. and Angel, E. 2003. The FFT on a GPU. In Proceedings of the ACM SIGGRAPH/EUROGRAPHICS conference on graphics hardware, 112–119.
    4. Murshudov, G. N., Vagin, A. A., and Dodson, E. J. 1997. Refinement of Macromolecular Structures by the Maximum-Likelihood Method. Acta Crystallographica D53, 240–255.
    5. Thompson, C. J., Hahn, S. and Oskin, M. 2002. Using modern graphics architectures for general-purpose computing: a framework and analysis, Proceedings of the 35th annual ACM/IEEE international symposium on Microarchitecture, 306–317. IEEE Computer Society Press, 2002.


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