“Subanosecond pixel rendering with million transistor chips” by Gharachorloo, Gupta, Hokenek, Balasubramanian, Bogholtz, et al. …

  • ©Nader Gharachorloo, Satish Gupta, Erden Hokenek, Peruvemba Balasubramanian, Bill Bogholtz, Christian Mathieu, and Christos Zoulas




    Subanosecond pixel rendering with million transistor chips



    The desire for higher performance and higher resolution continuously increases the pixel update rates needed in high performance graphics systems. The increasing density of memory chips on the other hand reduces the pixel update rate that can be provided by the frame buffer. We present the design of a VLSI chip and a graphics system that can sustain sub-nanosecond pixel rendering rates for three-dimensional polygons and can be used to render about a million Z-Buffered and Gourard shaded polygons per second. The chip has been designed at the IBM Research Division’s Thomas J. Watson Research Center.


    1. S. Demetrescu. High Speed Image Rastcrization Using Scan Line Access Memories. Proc. 1985 Chapel Hill Conference on VLSI, pages 221-243, Computer Science Press, 1985.
    2. H. Fuchs and J. Poulton. Pixel Planes: A VLSl-Oriented Design for a Raster Graphics Engine. VLSI Design, 2(3):20-28, 3rd. Quarter 1981.
    3. A. Garcia. ACE: A High Performance Multiprocessor Workstation, IBM Internal Communication, IBM Thomas J. Watson Research Center, 1987.
    4. N. Gharachorloo. Super Buffer: A systolic VLSI Graphics Engine for Real Time Raster Image Generation, Ph.D. Thesis, Electrical Engineering Department, Cornell Univ., Ithaca, NY. August 1985.
    5. N. Gharachorloo, S. Gupta, E. Hokenek, P. Balasubramanian, W. Bogholtz, C. Mathieu, and C. Zoulas. A Million Transistor Systolic Array Graphics Engine. Proceedings of International Conference on Systolic Arrays, San Diego, May 1988.
    6. N. Gharachorloo and C. Pottle. SUPER BUFFER: A Systolic VLSI Graphics Engine for Real Time Raster Image Generation. Proc. 1985 Chapel Hill Conference on VLSI, pages 285-305, Computer Science Press, 1985.
    7. J.H. Jackson. Dynamic Scan-converted images with a Frame Buffer Display Device. Computer Graphics, 14(3):163-169, July 1980.
    8. Bart Locanthi. Object Oriented Raster Displays. Proceedings of Caltech Conference on VLSI, pages 215-225, January 1979.
    9. A.J. Myers. An Efficient Visible Surface Program, Ohio State University, Report to the NSF, July 1975.
    10. H. Niimi, Y. Imai, M. Murakami, S. Tomita, and H. Hagiwara. A Parallel Processor System for Three Dimensional Color Graphics. Computer Graphics, 18(3):67-76, July 1984.
    11. R.W. Swanson and L.J. Thayer. A Fast Shaded- Polygon Renderer. Computer Graphics, 20(4):95-101, August 1986.
    12. G.S. Watkins. A Real Time Visible Surface Algorithm, University of Utah, Computer Science Department, June 1970.
    13. Richard Weinberg. Parallel Processing Image Synthesis and Anti-Aliasing. Computer Graphics, 15(3):55-61, August 1981.
    14. Daniel S. Whelan. A Rectangular Area Filling Display System Architecture. Computer Graphics, 16(3):147-153, July 1982.

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