“Larrabee: a many-core x86 architecture for visual computing” by Seiler, Carmean, Sprangle, Forsyth, Abrash, et al. …

  • ©Larry Seiler, Doug Carmean, Eric Sprangle, Tom Forsyth, Michael Abrash, Pradeep Dubey, Stephen Junkins, Adam Lake, Jeremy Sugerman, Robert Cavin, Roger Espasa, Ed Grochowski, Toni Juan, and Patrick (Pat) Hanrahan


Abstract:


    This paper presents a many-core visual computing architecture code named Larrabee, a new software rendering pipeline, a manycore programming model, and performance analysis for several applications. Larrabee uses multiple in-order x86 CPU cores that are augmented by a wide vector processor unit, as well as some fixed function logic blocks. This provides dramatically higher performance per watt and per unit of area than out-of-order CPUs on highly parallel workloads. It also greatly increases the flexibility and programmability of the architecture as compared to standard GPUs. A coherent on-die 2nd level cache allows efficient inter-processor communication and high-bandwidth local data access by CPU cores. Task scheduling is performed entirely with software in Larrabee, rather than in fixed function logic. The customizable software graphics rendering pipeline for this architecture uses binning in order to reduce required memory bandwidth, minimize lock contention, and increase opportunities for parallelism relative to standard GPUs. The Larrabee native programming model supports a variety of highly parallel applications that use irregular data structures. Performance analysis on those applications demonstrates Larrabee’s potential for a broad range of parallel computation.

References:


    1. Akenine-Möller, T., Haines, E. 2002. Real-Time Rendering. 2nd Edition. A. K. Peters. Google ScholarDigital Library
    2. Aila, T., Laine, S. 2004. Alias-Free Shadow Maps. In Proceedings of Eurographics Symposium on Rendering 2004, Eurographics Association. 161–166. Google ScholarCross Ref
    3. Alpert, D., Avnon, D. 1993. Architecture of the Pentium Microprocessor. IEEE Micro, v.13, n.3, 11–21. May 1993. Google ScholarDigital Library
    4. AMD. 2007. Product description web site: ati.amd.com/products/Radeonhd3800/specs.html.Google Scholar
    5. Bader, A., Chhugani, J., Dubey, P., Junkins, S., Morrison T., Ragozin, D., Smelyanskiy. 2008. Game Physics Performance On Larrabee Architecture. Intel whitepaper, available in August, 2008. Web site: techresearch.intel.com.Google Scholar
    6. Bavoil, L., Callahan, S., Lefohn, A., Comba, J. Silva, C. 2007. Multi-fragment effects on the GPU using the k-buffer. In Proceedings of the 2007 Symposium on Interactive 3D Graphics and Games (Seattle, Washington, April 30 – May 02, 2007). I3D 2007. ACM, New York, NY, 97–104. Google ScholarDigital Library
    7. Blumofe, R., Joerg, C., Kuszmaul, B., Leiserson, C., Randall, K., Zhou, Y. Aug. 25, 1996. Cilk: An Efficient Multithreaded Runtime System. Journal of Parallel and Distributed Computing, v. 37, i. 1, 55–69. Google ScholarDigital Library
    8. Blythe, D. 2006. The Direct3D 10 System. ACM Transactions on Graphics, 25, 3, 724–734. Google ScholarDigital Library
    9. Bookout, D. July, 2007. Shadow Map Aliasing. Web site: www.gamedev.net/reference/articles/article2376.asp.Google Scholar
    10. Buck, I., Foley, T., Horn, D., Sugerman, J., Fatahalian, K., Houston, M., and Hanrahan, P. 2004. Brook for GPUs: stream computing on graphics hardware. ACM Transactions on Graphics, v. 23, n. 3, 777–786. Google ScholarDigital Library
    11. Callahan, S., Ikits, M., Comba, J., Silva, C. 2005. Hardwareassisted visibility sorting for unstructured volume rendering. IEEE Transactions on Visualization and Computer Graphics, 11, 3, 285–295 Google ScholarDigital Library
    12. Chandra, R., Menon, R., Dagum, L., Kohr, D, Maydan, D., McDonald, J. 2000. Parallel Programming in OpenMP. Morgan Kaufman. Google ScholarDigital Library
    13. Chen, M., Stoll, G., Igehy, H., Proudfoot, K., Hanrahan P. 1998. Simple models of the impact of overlap in bucket rendering. In Proceedings of the ACM SIGGRAPH/EUROGRAPHICS Workshop on Graphics Hardware (Lisbon, Portugal, August 31 – September 01, 1998). S. N. Spencer, Ed. HWWS ’98. ACM, New York, NY, 105–112. Google ScholarDigital Library
    14. Chen, Y., Chhugani, J., Dubey, P., Hughes, C., Kim, D., Kumar, S., Lee, V., Nguyen A., Smelyanskiy, M. 2008. Convergence of Recognition, Mining, and Synthesis Workloads and its Implications. In Procedings of IEEE, v. 96, n. 5, 790–807.Google Scholar
    15. Chuvelev, M., Greer, B., Henry, G., Kuznetsov, S., Burylov, I., Sabanin, B. Nov. 2007. Intel Performance Libraries: Multicore ready Software for Numeric Intensive Computation. Intel Technology Journal, v. 11, i. 4, 1–10.Google Scholar
    16. Cohen, J., Lin., M., Manocha, D., Ponamgi., D. 1995. I-COLLIDE: An Interactive and Exact Collision Detection System for Large-Scale Environments. In Proceedings of 1995 Symposium on Interactive 3D Graphics. SI3D ’95. ACM, New York, NY, 189–196. Google ScholarDigital Library
    17. Eldridge, M. 2001. Designing Graphics Architectures Around Scalability and Communication. PhD thesis, Stanford. Google ScholarDigital Library
    18. Foley, J., Van Dam, A., Feiner, S., Hughes, J. 1996. Computer Graphics: Principles and Practice. Addison Wesley. Google ScholarDigital Library
    19. Fuchs, H., Poulton, J., Eyles, J., Greer, T., Goldfeather, J., Ellsworth, D., Molnar, S., Turk, G., Tebbs, B., Israel, L. 1989. Pixel-planes 5: a heterogeneous multiprocessor graphics system using processor-enhanced memories. In Computer Graphics (Proceedings of ACM SIGGRAPH 89), ACM, 79–88. Google ScholarDigital Library
    20. Ghuloum, A., Smith, T., Wu, G., Zhou, X., Fang, J., Guo, P., So, B., Rajagopalan, M., Chen, Y., Chen, B. November 2007. Future-Proof Data Parallel Algorithms and Software on Intel Multi-Core Architectures. Intel Technology Journal, v. 11, i. 04, 333–348.Google Scholar
    21. Gilbert, E., Johnson, D., Keerthi, S. 1988. A fast procedure for computing the distance between complex objects in three-dimensional space. IEEE Journal of Robotics and Automation, 4, 2, 193–203.Google ScholarCross Ref
    22. GPGPU. 2007. GPGPU web site: www.gpgpu.org.Google Scholar
    23. Greene, N. 1996. Hierarchical polygon tiling with coverage masks, In Proceedings of ACM SIGGRAPH 93, ACM Press/ACM SIGGRAPH, New York, NY, Computer Graphics Proceedings, Annual Conference Series, ACM, 65–64. Google ScholarDigital Library
    24. Grochowski, E., Ronen, R., Shen, J., Wang, H. 2004. Best of Both Latency and Throughput. 2004 IEEE International Conference on Computer Design (ICCD ’04), 236–243. Google ScholarDigital Library
    25. Gwennap, L. 1995. Intel’s P6 Uses Decoupled Superscalar Design. Microprocessor Report. v. 9, n. 2, Feb. 16, 1995.Google Scholar
    26. Hsieh, E., Pentkovski, V., Piazza, T. 2001. ZR: A 3D API Transparent Technology For Chunk Rendering. In Proceedings of the 34th Annual ACM/IEEE International Symposium on Microarchitecture (Austin, Texas, December 01 – 05, 2001). International Symposium on Microarchitecture. IEEE Computer Society, Washington, DC, 284–291. Google ScholarDigital Library
    27. Hughes, C. J., Grzeszczuk, R., Sifakis, E., Kim, D., Kumar, S., Selle, A. P., Chhugani, J., Holliman, M., and Chen, Y. 2007. Physical simulation for animation and visual effects: parallelization and characterization for chip multiprocessors. In Proceedings of the 34th Annual international Symposium on Computer Architecture (San Diego, California, USA, June 09 – 13, 2007). ISCA ’07. ACM, New York, NY, 220–231. Google ScholarDigital Library
    28. IEEE Std. 1003.1, 2004 Edition. Standard for Information Technology – Portable Operating System Interface (POSIX) System Interfaces. The Open Group Technical Standard Base Specifications. Issue 6.Google Scholar
    29. Jacobsen, T. 2001. Advanced Character Physics. Proc. Game Developers Conference 2001, 1–10.Google Scholar
    30. Johnson, G. S., Lee, J., Burns, C. A., Mark, W. R. 2005. The irregular Z-buffer: Hardware acceleration for irregular data structures. ACM Transactions on Graphics. 24, 4, 1462–1482. Google ScholarDigital Library
    31. Kelley, M., Gould, K., Pease, B., Winner, S., Yen, A. 1994. Hardware accelerated rendering of CSG and transparency. In Proceedings of SIGGRAPH 1994, ACM Press/ACM SIGGRAPH, New York, NY, Computer Graphics Proceedings, Annual Conference Series, ACM, 177–184. Google ScholarDigital Library
    32. Kelley, M., Winner, S., Gould, K. 1992. A Scalable Hardware Render Accelerator using a Modified Scanline Algorithm. In Computer Graphics (Proceedings of ACM SIGGRAPH 1992), SIGGRAPH ’92. ACM, New York, NY, 241–248. Google ScholarDigital Library
    33. Kessenich, J., Baldwin, D., Rost, R. The OpenGL Shading Language. Version 1.1. Sept. 7, 2006. Web site: www.opengl.org/registry/doc/GLSLangSpec.Full.1.20.8.pdfGoogle Scholar
    34. Khailany, B., Dally, W., Rixner, S., Kapasi, U., Mattson, P., Namkoong, J., Owens, J., Towles, B., Chang, A. 2001. Imagine: Media Processing with Streams. IEEE Micro, 21, 2, 35–46. Google ScholarDigital Library
    35. Kongetira, P., Aingaran, K., Olukotun, K. Mar/Apr 2005. Niagara: A 32-way multithreaded SPARC Processor. IEEE Micro. v. 25, i. 2. 21–29. Google ScholarDigital Library
    36. Lake, A. 2005. Intel Graphics Media Accelerator Series 900 Developer’s Guide. Version 2.0. Web site:download.intel.com/ids/gma/Intel_915G_SDG_Feb05.pdf.Google Scholar
    37. Lloyd, B., Govindaraju, N., Molnar, S., Manocha, D. 2007. Practical logarithmic rasterization for low-error shadow maps. In Proceedings of the 22nd ACM SIGGRAPH/EUROGRAPHICS Symposium on Graphics Hardware, 17–24. Google ScholarDigital Library
    38. Mark, W., Glanville, S., Akeley, K., Kilgard, M. 2003. Cg: A System for Programming Graphics Hardware in a C-like Language, ACM Transactions on Graphics, v. 22, n. 3, 896–907. Google ScholarDigital Library
    39. Microsoft. 2007. Microsoft Reference for HLSL. Web site: msdn2.microsoft.com/en-us/library/bb509638.aspx.Google Scholar
    40. Molnar, S., Cox, M., Ellsworth, D., and Fuchs, H. 1994. A Sorting Classification of Parallel Rendering. IEEE Computer Graphics and Applications, v.14, n. 4, July 1994, 23–32. Google ScholarDigital Library
    41. Molnar, S., Eyles, J., Poulton, J. 1992. Pixelflow: High Speed Rendering Using Image Composition. Computer Graphics (Proceedings of SIGGRAPH 92), v. 26 n. 2, 231–240. Google ScholarDigital Library
    42. Morein, S. 2000. ATI Radeon HyperZ Technology. Presented at Graphics Hardware 2000. Web site:www.graphicshardware.org/previous/www_2000/presentations/ATIHot3D.pdf.Google Scholar
    43. Nickolls, J., Buck, I., Garland, M. 2008. Scalable Parallel Programming with CUDA. ACM Queue, 6, 2, 40–53. Google ScholarDigital Library
    44. Nvidia. 2008. Product description web site:www.nvidia.com/object/geforce_family.html.Google Scholar
    45. Owens, J., Luebke, D., Govindaraju, N., Harris, M., Kruger, J., Lefohn, A., Purcell, T. 2007. A Survey of General Purpose Computation on Graphics Hardware. Computer Graphics Forum. v.26, n. 1, 80–113.Google Scholar
    46. Pham D., Asano, S., Bolliger, M., Day, M., Hofstee, H., Johns., C., Kahle, J., Kameyama, A., Keaty, J., Masubuchi, Y., Riley, M., Shippy, D., Stasiask, D., Suzuodi, M., Wang, M., Warnock, J., Weitzel, S., Wendel, D., Yamazaki, T., Yazawa, K. 2005. The Design and Implementation of a First Generation CELL Processor. IEEE International Solid-State Circuits Conference. 184–186.Google ScholarCross Ref
    47. Pharr, M. 2006. Interactive Rendering in the Post-GPU Era. Presented at Graphics Hardware 2006. Web site:www.pharr.org/matt/.Google Scholar
    48. Pineda, J. 1988. A Parallel Algorithm for Polygon Rasterization. In Computer Graphics (Proceedings of ACM SIGGRAPH 88), 22, 4, 17–20. Google ScholarDigital Library
    49. Power VR. 2008. Web site:www.imgtec.com/powervr/products/Graphics/index.asp.Google Scholar
    50. Pollack, F. 1999. New Microarchitecture Challenges for the Coming Generations of CMOS Process Technologies. Micro32. Google ScholarDigital Library
    51. Reinders, J., 2007. Intel Threading Building Blocks: Outfitting C++ for Multi-core Processor Parallelism. O’Reily Media, Inc. Google ScholarDigital Library
    52. Reshetov A., Soupikov, A., Hurley, J. 2005. Multi-level Ray Tracing Algorithm. ACM Transactions on Graphics, 24, 3, 1176–1185. Google ScholarDigital Library
    53. Rost, R. 2004. The OpenGL Shading Language. Addison Wesley. Google ScholarDigital Library
    54. Shevtsov, M., Soupikov, A., Kapustin, A. 2007. Ray-Triangle Intersection Algorithm for Modern CPU Architectures. In Proceedings of GraphiCon 2007, 33–39.Google Scholar
    55. Stevens, A. 2006. ARM Mali 3D Graphics System Solution. Web site:www.arm.com/miscPDFs/16514.pdf.Google Scholar
    56. Stoll, G., Eldridge, M., Patterson, D., Webb, A., Berman, S., Levy, R., Caywood, C., Taveira, M., Hunt, S., Hanrahan, P. 2001. Lightning 2: A High Performance Display Subsystem for PC Clusters. In Computer Graphics (Proceedings of ACM SIGGRAPH 2001), ACM, 141–148. Google ScholarDigital Library
    57. Torborg, J., Kajiya, J. 1996. Talisman Commodity Realtime 3D Graphics for the PC. In Proceedings of ACM SIGGRAPH 1996, ACM Press/ACM SIGGRAPH, New York. Computer Graphics Proceedings, Annual Conference Series, ACM, 353–363. Google ScholarDigital Library
    58. Wexler, D., Gritz, L., Enderton, E., Rice, J. 2005. GPU-accelerated high-quality hidden surface removal. In Proceedings of the ACM SIGGRAPH/EUROGRAPHICS Conference on Graphics Hardware (Los Angeles, California, July 30 – 31, 2005). HWWS ’05, ACM, New York, NY, 7–14. Google ScholarDigital Library


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