“A scalable hardware render accelerator using a modified scanline algorithm” by Kelley, Winner and Gould
Conference:
Type(s):
Title:
- A scalable hardware render accelerator using a modified scanline algorithm
Presenter(s)/Author(s):
Abstract:
No abstract available.
References:
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6. Foley, James, A. van Dam, S. Feiner and J. Hughes, “Computer Graphics Principles and Practice, 2nd Edition”, Addison-Wesley, 1990, 96-99 (basic scan conversion), 201-283 (transformation), 680-685 (scanline algorithms), 885-887 (scanline rasterization)
7. Fournier, Alain and D. Fussell, “On the Power of the Frame Buffer”, Transactions on Graphics, Vol. 7, No. 2, April 1988, 103-128
8. Fuchs, Henry and J. Poulton, “Pixel-Planes: A VLSI- Oriented Design for a Raster Graphics Engine”, Computer Graphics, Vol. 15, No. 3, August 1981, 80-81
9. Gharachorloo, Nader, S. Gupta, R. Sproul} and I. Sutherland, “A Characterization of Ten Rasterization Techniques”, Computer Graphics, Vol. 23, No. 3, July 1989, 355-368
10. Haeberli, Paul and K. Akeley, “the Accumulation Buffer: Hardware Support for High-Quality Rendering”, Computer Graphics, Vol. 24, No. 4, August 1990, 309-318
11. Kirk, David and D. Voorhies, ‘The Rendering Architecture of the DN10000VS”, Computer Graphics, Vol. 24, No. 4, August 1990, 299-307
12. Myers, A. J., “An Efficient Visible Surface Program”, Report to the National Science Foundation, Computer Graphics Research Group, Ohio State University, Columbus, OH, July 1975
13. Niimi, Haruo, Y. Imai, M. Murakami, S. Tomita and H. Hagiwara, “A Parallel Processor System for Three- Dimensional Color Graphics”, Computer Graphics, Vol. 18, No. 3, July 1984, 67-76
14. Rhoden, Desi and C. Wilcox, “Hardware Acceleration for Window Systems”, Computer Graphics, Vol. 23, No. 3, July 1989, 61-67
15. Watkins, G. “A Real-Time Visible Surface Algorithm”, Computer Science Department, University of Utah, UTECH-CSC-70-101, June 1970
