MASSCOMP

SIGGRAPH 1987

MASSCOMP’s MC5000 family of multiprocessor systems will demonstrate several applications which take advantage of unique capabilities in integrated data acquisition imaging and graphics. MASSCOMP will display medical imaging and molecular modeling on the Helios graphics accelerator, an industry leader in 3-D graphics performance. Come and use Laboratory Workbench, the data acquisition interface, to set up your own experiment to collect data and display the results in real-time.

SIGGRAPH 1986

The Aurora/Independent Graphics processor will be displayed on an MC5600 Micro Supercomputer. Aurora/IGP is a high-performance multibus boardset designed for scientific and engineering applications such as simulation, CAD, imaging and mapping. The Helios/Hierarchical Modeling Accelerator will be displayed on an MC5600 with Lightning Floating Point Accelerator. Helios/HMA is a 3-D processor with proprietary circuitry for high-speed modeling, shaded fill and hierarchical segment/object execution.

SIGGRAPH 1985

MASSCOMP will display a family of systems for scientific and technical markets using MASSCOMP’s Virtual Memory RTU. Systems on display include an 8-slot deskside, a 15-slot deskside dual processor system and a large cabinet configuration system each supporting high resolution monochrome and color graphics, Ethernet LAN, integrated array, and floating point processors. Each of the systems will be running engineering design application in mechanical or electronics.

SIGGRAPH 1984

MC-500 and WorkStation-500 both support a Real-Time virtual memory UNIX-based operating system. Both products are designed as 32-bit VLSI CPU’s with 4Kb data/address cache and up to 6 Megabytes of ECC memory. An array processor and a high performance floating point processor can optionally be configured for single and double precision engineering computations. The MC-500 additionally features a Data Acquisition and Control processor which enables analog acquisition (12 bit) at a million samples per second. A highly flexible performance architecture offloads the CPU, and performs graphics functions, Ethernet protocol work, each in a separate microprocessor