“Embree ray tracing kernels for CPUs and the Xeon Phi architecture” by Woop, Feng, Wald and Benthin

  • ©Sven Woop, Louis Feng, Ingo Wald, and Carsten Benthin

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    Embree ray tracing kernels for CPUs and the Xeon Phi architecture

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Abstract:


    Modern CPUs achieve high computational throughput by implementing increasingly wide SIMD vector units (such as 8-wide AVX or 16-wide SIMD for the Xeon Phi instructions). Achieving optimal performance on these architectures requires leveraging these wide SIMD vector units effectively. We present Embree [Ernst and Woop 2011], an open source ray tracing library developed to show performance-focused graphics programmers how to take full advantage of multiple cores and wide SIMD units in the context of ray tracing. Embree features spatial acceleration structures and traversal algorithms that are optimized for CPUs and the Intel Xeon Phi architecture. In particular, Embree supports hybrid ray packet/single ray traversal algorithms—optimized for both CPUs and Xeon Phi—that are designed to handle both coherent and incoherent workloads efficiently [Benthin et al. 2012]. While a first version of Embree originally focused only on single ray traversal on SSE- or AVX-enabled CPUs, this talk specifically covers the upcoming Embree 2.0 release that explicitly also supports the Xeon Phi architecture, adds support for packet tracing, two level hierarchies, partial scene updates, dynamic content, and virtual intersectors for user defined primitives.

References:


    1. Benthin, C., Wald, I., Woop, S., Ernst, M., and Mark, W. R. 2012. Combining single and packet-ray tracing for arbitrary ray distributions on the intel mic architecture. IEEE Transactions on Visualization and Computer Graphics 18, 9, 1438–1448.
    2. Ernst, M., and Woop, S., 2011. Embree: Photo-Realistic Ray Tracing Kernels. http://software.intel.com/en-us/articles/embree-photo-realistic-ray-tracing-kernels, June.
    3. Pharr, M., and Mark, W. 2012. ISPC: A SPMD Compiler for high-performance CPU Programming. In Innovative Parallel Computing (InPar), 2012, 1–13.


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